1. Field of the Invention
The present invention relates generally to audio/video (AV) systems, and more specifically, to a method and system for synchronizing downstream video data asynchronously sampled from a video signal.
2. Background of the Invention
Digital audio and video systems are prevalent in the areas of home entertainment, professional production of multimedia and computer reproduction and generation of multimedia sources. In particular, systems that record a video stream are frequently coupled to source devices such as cameras and also produced from AV playback devices such as DVD and CD players.
It is necessary to receive, resynchronize and sometimes resample a video signal for recording or processing purposes, whether by a general-purpose computing device, a dedicated video processing device, or a dedicated video recording device. The source video rate may not match the recording or processing video rate, and even if the rates did match, it would be desirable to asynchronously sample the video signal, as will be pointed out in detail below.
Traditionally, video clock sources are sampled synchronously, with a source-locked video clock. The source-locked video clock used to sample the video signal is generated by a phase-lock loop (PLL) that locks to the incoming line rate, frame rate, or combination of both. While source-locking provides a video clock that is free of drift or “slipping”—at least for relatively clean video signals, video degradation is present in the sampled video due to jitter and other noise that is introduced or cannot be removed by the PLL. In particular, most composite video signals have events such as vertical blanking interval (VBI) that require special circuits in the PLL to avoid disrupting the lock signal and the frequency of the video clock signal of the source may vary from source to source over a fairly wide margin. PLLs that handle such variable signals and disruptive events require a reasonably wide loop bandwidth for capture and lock retention.
In general, less noise and jitter is generally provided by asynchronously sampling a signal, rather than synchronously sampling a signal, as a very stable local reference clock may be employed. A stable sampling clock can be designed to minimize environmentally-introduced noise, be ideally terminated to the sample clock input and be otherwise optimized for the video sampling circuit. However, asynchronous sampling of signals with accurate phase preservation requires a high oversampling factor, which is typically impractical for video sources. In particular, the recovery of the synchronization elements in a video signal (such as the luminance and chrominance carriers that require phase accuracy on the order of two degrees or less) would require a sampling clock on the order of 1 Ghz in order to completely preserve the video signal.
When the desired output video rate does not match the incoming line clock rate, it also is necessary to not only synchronize the output video data, but the data must be converted to the new rate. As pointed out above, there are significant advantages to asynchronously sampling a video signal, and further advantages are present in sample rate conversion schemes, as the more stable and noise-free sampling clock on which the samples are based leads to more stable input data for the sample rate conversion process. Any jitter or frequency variation in the sampling timebase causes error in the conversion due to uneven sample spacing in the conversion input data.
Therefore, it would be desirable to provide a method and system for synchronizing downstream video information obtained by asynchronously sampling a video source. It would further be desirable to provide sample rate conversion of asynchronously sampled video data.